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II-2 EPSON S1C6S2N7 TECHNICAL SOFTWARE

CHAPTER 1: CONFIGURATION

ROM Map

The S1C6S2N7 has a built-in mask ROM with a capacity of

1,536 steps × 12 bits for program storage. The configuration

of the ROM is shown in Figure 1.2.1.

1.2

00H step

0FH step

10H step

FFH step

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

0 page

1 page

2 page

3 page

4 page

5 page

01H step

Fig. 1.2.1

Configuration of built-in ROM

1 2 ... 107 108 109 110 111 112 113 114 115 116 117 ... 190 191

S1C6S2N7 1
Technical Hardware 7
CONTENTS 10
Hardware 11
INTRODUCTION 13
CHAPTER 1 13
Features 14
Core CPU S1C6200A 15
Pin Layout Diagram 16
Pin Description 17
Power Supply 18
Fig. 2.1.2 19
External elements when 19
LCD system regulated 19
Initial Reset 20
Table 2.2.1 21
Input port combinations 21
Table 2.2.2 21
Simultaneous high input 21
Test Pin (TEST) 22
CPU, ROM, RAM 23
CHAPTER 3 23
Fig. 3.2.1 24
ROM configuration 24
PERIPHERAL CIRCUITS 25
AND OPERATION 25
Table 4.1.1(a) I/O memory map 26
Table 4.1.1(b) I/O memory map 27
Table 4.1.1(c) I/O memory map 28
Table 4.1.1(d) I/O memory map 29
Table 4.1.1(e) I/O memory map 30
Oscillation Circuit 31
Input Ports (K00–K03) 32
Data bus 33
Mask option 34
Control of input port 35
Output Ports (R00–R03) 37
EPSON I-27 39
Control of output 40
R00 register 41
FOUT output 41
R01 (R00) register 42
BUZZER output 42
I/O Ports (P00–P03) 43
I/O control register 44
Control of I/O port 44
Configuration of LCD 47
Frame frequency 48
Fig. 4.6.2 49
Drive waveform for 49
1/3 duty (1/3 bias) 49
Fig. 4.6.3 50
1/2 duty (1/3 bias) 50
LCD lighting status 51
Fig. 4.6.7 53
LCD static drive waveform 53
Fig. 4.6.8 54
Segment allocation 54
EPSON I-43 55
Fig. 4.6.9 56
Clock Timer 57
Frequency 58
Register 58
Control of clock 59
Stopwatch Timer 61
Count-up pattern 62
Interrupt function 63
Control of stopwatch 64
EPSON I-53 65
Configuration of SVD 67
Operation of SVD 69
Operation of heavy 70
Control of SVD cir 71
Stepping Motor Driver 73
Drive pulse 74
Control of motor 75
Interrupt and HALT 77
Interrupt flag 78
Interrupt factors 79
Specific masks and 80
CPU system clock 81
Control of interrupt 82
EPSON I-71 83
BASIC EXTERNAL WIRING DIAGRAM 84
CHAPTER 5 84
S1C6S2N7/6S2A7 85
6S2B7/6S2L7 85
6.1 Absolute Maximum Rating 86
S1C6S2A7 87
S1C6SL27 88
S1C6S2B7 88
6.3 DC Characteristics 89
EPSON I-79 91
EPSON I-81 93
EPSON I-83 95
S1C6SL27/S1C6S2B7 97
S1C6S2N7 (CR oscillation) 98
S1C6S2A7 (CR oscillation) 98
S1C6S2B7 (CR oscillation) 98
Unless otherwise specified 99
CD=built-in, Ta=25°C 99
7.1 Plastic Package 100
QFP6-60pin 101
8.1 Diagram of Pad Layout 102
8.2 Pad Coordinates 103
Technical Software 105
Software 109
S1C6S2N7 Block Diagram 111
Program start address 112
Interrupt vector area 112
Program area 112
Interrupt Vectors 113
Data Memory Map 114
EPSON II-5 115
CHAPTER 1: CONFIGURATION 115
EPSON II-9 119
INITIAL RESET 120
CHAPTER 2 120
EPSON II-11 121
CHAPTER 2: INITIAL RESET 121
Initialize Program Example 122
Enable interrupt 123
Reset register flags 123
Fig. 2.2.1 123
Input Ports 124
Control of 125
Examples of input 125
Disable interrupt 126
Set address of port 126
Output Ports3.2 127
Examples of output 128
EPSON II-19 129
Special Use Output Ports3.3 130
Control of the spe 131
Examples of special 132
EPSON II-23 133
3.4 I/O Ports 134
Examples of I/O port 136
EPSON II-27 137
LCD Driver3.5 139
Control of the LCD 140
Fig. 3.5.3 141
7-segment LCD assignment 141
Fig. 3.5.2 141
1/1 duty drive control 141
(1/3 bias) 141
Examples of 142
LCD driver control 142
D3 D2 D1 D0 143
3.6 Timer 144
Control of the timer 145
Examples of timer 146
EPSON II-37 147
3.7 Stopwatch Timer 148
Control of the stop 149
Examples of stop 150
B register 151
A register 151
SVD circuit and 152
Control of the SVD 153
Example of SVD 153
Heavy load protec 154
EPSON II-45 155
Examples of heavy 156
EPSON II-47 157
Fig. 3.8.4 158
Flowchart of operation 158
3.9 Motor Driver 159
Control of the motor 160
Examples of motor 160
3.10 Interrupt and Halt 161
Control of interrupts 163
Fig. 3.10.1 164
Input interrupt circuit 164
Fig. 3.10.2 165
Timer interrupt circuit 165
Fig. 3.10.3 166
Stopwatch interrupt circuit 166
Fig. 3.10.4 167
Port K input 168
Factor flag set Not set 168
Mask register 168
Active status 168
EPSON II-59 169
Fig. 3.10.6 170
Assignment of the interrupt 170
Table 3.10.2 171
Interrupt vector map 171
Fig. 3.10.7 172
Internal interrupt circuit 172
Examples of interrupt 173
EPSON II-65 175
CHAPTER 4 176
SUMMARY OF PROGRAMMING 176
EPSON II-69 179
EPSON II-71 181
Registers specified 183
EPSON II-75 185
EPSON II-77 187
EPSON II-79 189
Technical Manual 191

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